1. Field of the Invention
The present invention relates to interposer substrates, and, more particularly, to an interposer substrate used in a package having a stack structure and a method of fabricating the interposer substrate.
2. Description of Related Art
With the advancement in semiconductor packaging technology, a semiconductor device may be packaged in a variety of manners, in order to increase electrical functionality and reduce packaging space. For instance, a Package on Package (PoP) is developed having multiple packaging structures, each being stacked on top of the other. This type of package having the property of heterogeneous integration of a System in Package (SiP), is capable of incorporating and integrating various electronic components of different functions, such as memory, central processing unit, graphic processor, image processor, etc., in a package through stacking techniques, thereby is very suitable to be used in various low-profile electronic products.
Early stacked packages are formed by stacking memory packages (memory IC) over the logic packages (logic IC) via a plurality of solder balls. As the demand for compact-size and low-profile electronic products, the density of wiring on the memory package increases. The memory package is measured in nanometers; the distance between the contacts are further shortened. However, the distances between the logic packages are measured in micrometers, and cannot be reduced any further to comply with the distances between the memory packages. As a result, even a memory package with high density wiring is provided, there is no suitable logic package to go in concert with the memory package, thereby unable to achieve efficient production of the electronic products.
Accordingly, in order to overcome the above mentioned drawbacks, an interposer substrate 10 is disposed between a memory package 11 and a logic package 12. As shown in FIG. 1, the bottom of the logic package 12 is coupled to the logic package 12 having logic chips of greater pitches, while the top of the interposer substrate 10 is coupled to a memory package having a memory chip 110 of less pitches.
However, since in the stacked package 1 a plurality of solder balls 13 are used as a supporting and electrical means, if I/O number is increasing and the package size remains the same, the distance between each of the solder balls 13 needs to be shortened, which may easily cause short circuit as a result of bridging, and subsequently causing low yield and unsatisfactory reliability.
Thus, copper pillars are developed to replace the solder balls. The copper pillars have the advantage that they can hardly become deformed during the reflow process, which keeps the same height between each of the copper pillars, thereby preventing the bridging problem, so as to increase the product yield.
FIGS. 1A-1D are cross-sectional views showing a method of fabricating a conventional interposer substrate 10.
As shown in FIG. 1A, a plurality of vias 100 are formed penetrating the board 10′ such as a copper foil substrate.
As shown in FIG. 1B, two wiring layers 14 are formed on the two sides of the board 10, respectively, via copper foils 10a, and a plurality of conductive vias 15 are formed in the vias 100 and electrically connected with the wiring layer 14.
As shown in FIG. 1C, an insulative protection layer 16 is formed on the board 10′ and the wiring layers 14, and a portion of the wiring layers 14 is exposed and functions as conductive pads 140.
As shown in FIG. 1D, copper pillars 17 are disposed on the conductive pads 140.
However, a higher cost is required for the complex method in making the conventional interposer substrate 10 (such as forming the vias 100). Moreover, conductive layers 170 are required to be formed additionally for the electroplating process for forming the copper pillars 17 (on one side or two sides according to practical needs). Therefore, after the excessive conductive layer 170 is removed, it is common to have residual conductive materials of the conductive layer 170 remained, which interferes the conductivity of the copper pillars 17 (for instance the remaining conductive layer 170 may connect with the adjacent copper pillars 17, which causing short circuit), causing the overall conductivity to be deteriorated.
Moreover, the thickness of the interposer substrate 10 needs to take consideration of the board 10′ (that is the core layer) and may become limited (hard to be thinner). Hence, the thinner the thickness of the interposer substrate 10 is, the harder it is to be fabricated. Moreover, the problem such as damages to the board 10′ will be encountered.
In addition, there will be limitation for design of the line width/line space (L/S) of the wiring layer 14. In general, the smallest L/S that can be fabricated is 12/12 μm, but the yield may be influenced when L/S is anywhere lower than 25/25 μm.
Hence, there is an urgent need to solve the foregoing problems encountered in the prior art.